1. Field of the Invention
The present invention relates to a digital signal processor (DSP) suitable for filtering, reverberation addition processing, and so on.
2. Related Art
A DSP is a processor developed mainly for the purpose of executing product sum calculations at a high speed. For example, in the field of audio applications, the DSP is used for digital signal processing which requires the real time nature, such as filtering, reverberation addition processing, and so on for audio signals.
A DSP 100 illustrated in FIG. 4 is an example of this type of DSP. In FIG. 4, an input register 101 stores a digital signal to be processed by the DSP 100. Specifically, the DSP 100 is supplied with sample data such as an audio signal or the like every sampling period, and such sample data is supplied to the inside of the DSP 100 through the input register 101. A coefficient register 102 stores coefficients (filter coefficients) used in multiplication for a product sum calculation. A multiplier 103 executes the multiplication for the product sum calculation. An adder input selector 104, an adder 105, an accumulator input selector 106, and an accumulator 107 constitute a means for adding a multiplication result derived from the multiplier 103 to a so far derived calculation result to generate a target calculation result. A temporary memory 108, capable of simultaneous reading and writing, is used as a delay means for holding sample data or calculation results for an arbitrary time period. An external memory control circuit 109 is used when an external memory, not shown, is used as an additional delay means for controlling input/output of sample data and so on to and from the external memory. A main selector 110 controls the switching of a flow of sample data and calculation results, and an output register 111 stores a processed result to be outputted.
In the drawing, a variety of character strings written in lower-case alphabet letters are attached to some of the components described above. These character strings represent the names of control signals supplied to associated components when an instruction decoder, not shown, decodes instructions.
In the following, the operation of the DSP 100 will be described in connection with examples in which an FIR (Finite Impulse Response) filtering operation is performed and in which reverberation addition processing is performed.
(1) Operations when FIR Filtering is Performed:
Here, the operation of the DSP 100 will be described for an example in which the DSP 100 executes the FIR filtering operation expressed by the following equation: ##EQU1## where x(t-i) represents input sampling data in a sampling period i sampling periods before, y(t) represents the result of the FIR filtering operation in the current sampling period, and y(t-i) represents the result of the FIR filtering operation in a sampling period i sampling periods before. a.sub.i (i=0-64) and b.sub.i (i=0-62) are different filter coefficients, respectively.
FIG. 5 shows a list of an exemplary program for executing the FIR filtering operation mentioned above. For facilitating the explanation, a line number is added on the left side of each program line. While each line constituting the program includes a plurality of instructions, the instructions included on the same line are simultaneously executed in parallel. The functions provided by respective instructions are described below.
SEL xx: The execution of this instruction causes a selection signal msel to be supplied to the main selector 110 which responsively switches an input signal to be selected. Explaining more specifically how this instruction is used in connection with the program shown in FIG. 5 as an example, the execution of the SEL instruction causes the main selector 110 to select an input signal as follows:
SEL IN: select output data of the input register 101;
SEL ACC: select output data of the accumulator 107; and
SEL Txx: select output data of the temporary memory 108. In this case, since a read address tradr corresponding to xx is also supplied to the temporary memory 108 in addition to the selection signal msel, the contents at address xx in the temporary memory 108 is selected by the main selector 108.
MUL xx: this instruction sets data xx to the coefficient register 102, and a product sum calculation using the data xx is executed by the multiplier 103, the adder 105 and the accumulator 107. For example, an instruction "MUL C2" on the second line of the program shown in FIG. 5 supplies data C2 to the multiplier 103 through the coefficient register 102, instructs the multiplier 103 to multiply the data C2 by output data of the main selector 110, and instructs the adder 105 to add the result of this multiplication and output data of the accumulator 107. Then, the addition result of the adder 105 is written into the accumulator 107 through the accumulator input selector 106 when the program proceeds to the execution of instructions on the third line.
ACLR: this instruction clears the accumulator 107.
WT xx: This instruction supplies a write enable signal twe and a write address twadr corresponding to xx to the temporary memory 108, and writes output data of the main selector 110 into the temporary memory 108 at address xx.
OUTPUT: this instruction generates an output enable signal owe to deliver output data of the main selector 110 to the outside through the output register 111.
Next, the contents of specific processing executed by the exemplary program will be described. In this exemplary program, instructions on lines 0-63 are executed to perform the convolution operation of the first term in the aforementioned Equation 1, instructions on lines 64-128 are executed to perform the convolution operation of the second term and to add the result of the calculation of the first term and the result of the calculation of the second term. As sampling data x(t-i) (i=0-64) for previous 65 sampling periods are used in the calculation of the first term, the respective sampling data x(t)-x(t-63) are stored in the temporary memory 108 at corresponding addresses 63-0, respectively. Also, as calculation results y(t-i) (i=0-62) for previous 63 sampling periods are used in the calculation of the second term, respective calculation results y(t)-y(t-62) are stored in the temporary memory 108 at corresponding addresses 127-65, respectively. The processing for storing the sample data and calculation results into the temporary memory 108 as mentioned above will be described later. While each MUL instruction in the program uses data CO - C127, data C64 - CO correspond to the coefficients a.sub.i (i=0-64), and data C127 - C65 correspond to the coefficients bi (i=0-62).
In the following, the operation of the DSP 100 associated with the FIR filtering operation will be described along the program shown in FIG. 5.
In the DSP 100, the program shown in FIG. 5 is executed once every sampling period. First, on the 0th line of the program, sample data x(t-64) stored in the temporary memory 108 at address 0 is read and outputted through the main selector 110 (SEL TO). Also, the output data x(t-64) of the main selector 110 is multiplied by data CO (coefficient a.sub.64) (MUL CO), and the accumulator 107 is cleared (ACLR).
Next, turning to the first line, output data of the accumulator 107 (=0) is added to output data a.sub.64 x(t-64) of the multiplier 103 by the adder 105 and the sum is supplied to and written into the accumulator 107 from the adder 105. Also, sample data x(t-63) stored in the temporary memory 108 at address 1 is outputted through the main selector 108 (SEL T1), and this output data x(t-63) is written into the temporary memory 108 at address 0 (WT 0). Further, the multiplier 103 multiplies the output data x(t-63) of the main selector 110 by data C1 (coefficient a.sub.63) (MUL C1).
Next, turning to the second line, output data (=a.sub.64 x(t-64)) of the accumulator 107 is added to output data a.sub.63 x(t-63) of the multiplier 103 by the adder 105 and supplied from the adder 105 to the accumulator 107 and written into the accumulator 107. Also, sample data x(t-62) stored in the temporary memory 108 at address 2 is outputted through the main selector 110 (SEL T2), and this output data x(t-62) is written in the temporary memory 108 at address 1 (WT 1). Further, the multiplier 103 multiplies the output data x(t-62) of the main selector 110 by data C2 (coefficient a.sub.62) (MUL C2).
Next, by executing the next third line (not shown), the sum of output data (a.sub.64 x(t-64)+a.sub.63 (t-63)) of the accumulator 107 and output data a.sub.62 x(t-62) of the multiplier 103 is written into the accumulator 107.
Subsequently, the processing for accumulating the product of sample data x(t-i) and a coefficient a.sub.i in the accumulator 107 and the processing for shifting sample data x(t-i) to an address one number less than the current address in the temporary memory 108 are sequentially executed in a similar manner.
Then, turning to the 64.sup.th line, the input register 101 is selected by the main selector 110 (SEL IN), so that sample data x(t) in the current sampling period, stored in the input register 101, is written into the temporary memory 108 at address 63 through the main selector 110 (WT 63).
The sample data x(t) thus written into the temporary memory 108 is subsequently shifted from address 63 to address 62, from address 62 to address 61, and so on, each time a sampling period ends and the next sampling period begins. As a result of the shift operation performed as described above, a sequence of sample data for previous 64 sampling periods are stored in the temporary memory 108 from address 63 to address 0.
Also, on the 64.sup.th line of the program, the multiplier 103 multiplies the output data x(t) of the main selector 110 by data C64 (coefficient a.sub.0) (MUL C64). Then, turning to the next 65.sup.th line after completing the processing on the 64.sup.th line, the sum of output data of the accumulator 107 and output data a.sub.0 x(t) of the multiplier 103, i.e., the calculation result of the first term of the aforementioned Expression 1 is written into the accumulator 107.
Next, on the 65.sup.th line, a calculation result y(t-62) is read from address 65 of the temporary memory 108 and outputted through the main selector 110 (SEL T65). Then, the output data y(t-62) of the main selector 110 is multiplied by data C65 (coefficient b.sub.62) (MUL C65).
Turning next to the 66.sup.th line, output data of the accumulator 107, i.e., the sum of the result of the convolution operation of the first term in Equation 1 and output data b.sub.62 y(t-62) of the multiplier 103 is supplied from the adder 105 to the accumulator 107, and written into the accumulator 107. Also, the calculation result y(t-61) stored in the temporary memory 108 at address 66 is outputted through the main selector 110 (SEL T66), and this calculation result y(t-61) is written into the temporary memory 108 at address 65 (WT 65). Further, the multiplier 103 multiplies the output data y(t-61) by data C66 (coefficient b.sub.61) (MUL C66).
Then, by executing the next 67.sup.th line of the program (not shown), the sum of output data (=the result of the convolution operation of the first term in Equation 1+b.sub.12 y(t-62)) of the accumulator 107 and output data b.sub.61 y(t-61) of the multiplier 103 is written into the accumulator 107.
Subsequently, the processing for accumulating the product of a previous calculation result y(t-i) and a coefficient b.sub.i in the accumulator 107 and the processing for shifting a calculation result y(t-i) to an address one number less than the current address in the temporary memory 108 are sequentially executed in a similar manner.
At the time the 128.sup.th line of the program has been executed, the final calculation result y(t) of the aforementioned Equation 1 in the current sampling period is found in the accumulator 107. Then, on the 128.sup.th line, the final calculation result y(t) is outputted through the main selector 110 (SEL ACC), and written into the temporary memory 108 at address 127 (WT 127) as well as outputted to the outside through the output register 111 (OUTPUT).
Subsequently, every time the sampling period ends and the next sampling period begins, the foregoing processing is repeated.
Then, the calculation result y(t) written into the temporary memory 108 on the 128.sup.th line of the program is sequentially shifted from address 127 to address 126, from address 126 to address 125, and so on in the temporary memory 108 in each sampling period. As a result of this shift operation, the calculation results for previous 63 sampling periods are stored in the temporary memory 108 from address 127 to address 65.
(2) Operations when Reverberation Addition Processing is Performed:
Generally, the reverberation addition processing requires a sequence of sample data having a time length extremely longer as compared with the foregoing filtering operation or the like. FIG. 6 illustrates an FIR filtering operation for generating a reverberation sound digital signal from a sequence of sample data in a hardware implementation. In the drawing, z-.sup.1 represents a delay operation for delaying sample data by a time corresponding to one sample period. Also, M represents multiplication, and ADD addition. C.sub.0 -C.sub.n-1 are filter coefficients for adding reverberation.
In this reverberation addition processing, operations are performed for convoluting the coefficients C.sub.0 -C.sub.n-1 into respective sample data produced by delaying input sample data by T.sub.0, T.sub.1, T.sub.2, T.sub.n-1, respectively. While the number of sample data used in the convolution operation is n, it is necessary to previously store a much larger number of sample data than this for performing the delay operations shown in FIG. 6. However, since the temporary memory 108 has only a small capacity, such an immense number of sample data sequences cannot be stored therein. Thus, for the reverberation addition processing, a large capacity external memory is used as delay means for sample data. The external memory control circuit 109 in FIG. 4 is a means provided for delaying sample data using the external memory.
In the following, details of sample data delaying operations using an external memory 20 will be described with reference to FIG. 7.
First, the external memory control circuit 109 has a built-in counter which is down-counted by one every sampling period. In each sampling period, a count value of this counter is supplied to the external memory 20 as a write address. Also, in each sampling period, output data in the input register 101, i.e., input sample data x(t) from the outside is selected by the main selector 110, and this input sample data x(t) is supplied to the external memory 20 through the external memory control circuit 109. As a result, the sample data x(t) is written into an area corresponding to the write address in the external memory 20.
Similar operations are performed in each of subsequent sampling periods, whereby input sample data to the DSP 100 are sequentially written into the external memory 20 as the write address is sequentially decremented.
Additionally, in each sampling period, n sample data used for the reverberation addition processing are read from the external memory 20 in parallel with the writing of the input sample data.
More specifically, in one sampling period, an address generated by incrementing the write address by T.sub.0, an address generated by incrementing the write address by T.sub.1, . . . , an address generated by incrementing the write address by T.sub.n-1 are sequentially supplied to the external memory 20 as read addresses by the external memory control circuit 109. As a result, in the same sampling period, respective sample data stored in these addresses, i.e., sample data x(t-T.sub.0) a time T.sub.0 before the current sampling period, sample data x(t-T.sub.1) a time T.sub.1 before the current sampling period, . . . , sample data x(t-T.sub.n-1) a time T.sub.n-1 before the current sampling period are read from the external memory 20.
Then, with the configuration illustrated in FIG. 4, the coefficients C.sub.0 -C.sub.n-1 in FIG. 6 are convoluted into the respective sample data to generate sample data for reverberation sound. Incidentally, since the convolution operation is performed in a manner similar to that previously described in connection with the exemplary program, detailed explanation is omitted.
The conventional DSP described above uses an external memory dedicated to the delay operation for adding reverberation because the reverberation addition processing must be duly advanced in order to continuously generate reverberation sound in real time. However, if it is ensured that previous sample data required for the reverberation addition processing are supplied to the DSP without delay, the DSP can share a memory together with another device such that the shared memory is used for the delay operation instead of providing a dedicated external memory. If this can be realized, the number of parts will be reduced by those associated with the external memory, thus largely contributing to reducing the size and cost of an entire system equipped with a DSP. Generally, since the external memory requires the use of expensive dual port RAM devices for simultaneous read and write operations, the removal of the external memory, if possible, will result in a large economical effect.